1. Field of the Invention
This invention relates to computer systems. In particular, the invention relates to memory controllers.
2. Description of Related Art
Synchronous dynamic random access memories (SDRAM) provide fast access time to support high performance microprocessors. Normally, SDRAMs are available with various memory organizations, ranging from 16 Megabit (Mb) to 128 Mb. A SDRAM is addressed by a row address and a column address. The number of row address lines and the number of column address lines may be different. In addition, an SDRAM may also have multiple banks. As an example, a 16 Mb SDRAM may be organized as 1M.times.16 having 11 row address lines, 8 column address lines, and two banks.
In a typical high performance microprocessor system, the main memory consists of an array of SDRAMs of different organizations. The use of mixed memory devices provides flexibility and memory usage efficiency. An array of SDRAMs in the main memory consists of a number of rows. Each row of the SDRAM devices may correspond to a different device organization. One row may include SDRAM devices having one depth which supports one page size. Another row may include SDRAM devices having another depth which supports another page size.
In a system having mixed types of SDRAMs, traditional memory controllers cannot support all the available page sizes. Current SDRAM controller designs fix the page size either at the smallest supported page size or the smallest page size of all the installed rows in the memory array. This prevents the memory controller from taking advantage of the larger potential page sizes which may be installed.
Therefore, there is a need in the technology to provide a simple and efficient method to support different page sizes in mixed memory devices array organization.